Efficient FIR Filter Architectures Suitable for FPGA Implementation
نویسنده
چکیده
This paper describes efficient architectures for FIR filters. By exploiting the reduced complexity made possible by the use of two powers-of-two coefficients, these architectures allow the implementation of high sampling rate filters of significant length on a single field-programmable gate array (FPGA). The author can be contacted via e-mail at [email protected]. Portions of this work will be presented at ISCAS ’93 in Chicago, Illinois. This research is supported by the University of Kansas General Research allocation 3626-20-0038.
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